Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for over twenty years for interconnecting high I/O (input/output) count and area array solder bumps on the silicon chips to the base ceramic chip carriers, for example alumina carriers. The solder bump, typically a lead/tin alloy such as 95 Pb/5 Sn alloy, or a lead/indium alloy, such as 50 Pb/50 In, provides the means of chip attachment to the ceramic chip carrier for subsequent usage and testing. For example, see U.S. Pat. Nos. 3,401,126 and 3,429,040 to Miller and assigned to the assignee of the present application, for a further discussion of the controlled collapse chip connection (C4) technique of face down bonding of semiconductor chips to a carrier. Typically, a malleable pad of metallic solder is formed on the semiconductor device contact site and solder joinable sites are formed on the conductors on the chip carrier.
The device carrier solder joinable sites are surrounded by non-solderable barriers so that when the solder on the semiconductor device contact sites melts, surface tension of the molten solder prevents collapse of the joints and thus holds the semiconductor device suspended above the carrier. With the development of the integrated circuit semiconductor device technology, the sizes of individual active and passive circuit elements and gates have become very small, the number of circuit elements and gates in the integrated circuit has increased dramatically, and the integration of multiple functions on a single chip, with increasing numbers of circuits per chip, has increased explosively. This results in significantly larger chip sizes with larger numbers of I/O terminals. This trend will continue and will place increasingly higher demands on chip joining technology. An advantage of solder joining a device to a substrate is that the I/O terminals can be distributed over substantially the entire top surface of the semiconductor device. This allows an efficient use of the entire surface, which is more commonly known as area array bonding.
Usually the integrated circuit semiconductor devices are mounted on supporting substrates made of materials with coefficients of thermal expansion that differ from the coefficient of thermal expansion of the material of the semiconductor device, i.e. silicon. Normally the device is formed of monocrystalline silicon with a coefficient of thermal expansion of 2.5.times.10.sup.-6 per .degree.C. and the substrate is formed of a ceramic material, typically alumina with a coefficient of thermal expansion of 5.8.times.10.sup.-6 per .degree.C. or an organic substrate which can be either rigid or flexible material having a coefficient of thermal expansion ranging from 6.times.10.sup.-6 to 24.0.times.10.sup.-6 per .degree.C. In operation, the active and passive elements of the integrated semiconductor device inevitably generate heat resulting in temperature fluctuations in both the devices and the supporting substrate since the heat is conducted through the solder bonds. The devices and the substrate thus expand and contract in different amounts with temperature fluctuations, due to the different coefficients of thermal expansion. This imposes stresses on the relatively rigid solder terminals.
The stress on the solder bonds during operation is directly proportional to (1) the magnitude of the temperature fluctuations, (2) the distance of an individual bond from the neutral or central point (DNP), and (3) the difference in the coefficients of thermal expansion of the material of the semiconductor device and the substrate, and inversely proportional to the height of the solder bond, that is the spacing between the device and the support substrate. The seriousness of the situation is further compounded by the fact that as the solder terminals become smaller in diameter in order to accommodate the need for greater I/O density, the overall height decreases.
More recently, an improved solder interconnection structure with increased fatigue life has been disclosed in U.S. Pat. No. 4,604,644 to Beckham, et al. and assigned to the assignee of the present application, disclosure of which is incorporated herein by reference. In particular, U.S. Pat. No. 4,604,644 discloses a structure for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections where each solder connection is joined to a solder wettable pad on the device and a corresponding solder wettable pad on the support substrate, dielectric organic material disposed between the peripheral area of the device and the facing area of the substrate, which material surrounds at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of dielectric organic material.
The preferred material disclosed in U.S. Pat. No. 4,604,644 is obtained from a polyimide resin available commercially and sold under the trademark AI-10 by Amoco Corporation. AI-10 is formed by reacting a diamine such as p,p'diaminodiphenylmethane with trimellitic anhydride or acylchloride of trimellitic anhydride. The polymer is further reacted with .gamma.-amino propyl triethoxy silane (A1100) or .beta.-(3,4-epoxy cyclohexyl) ethyltrimethoxy silane (A-186) from Dow Corning. The coating material is described in IBM TDB September. 1970 P. 825.
The dielectric material is typically applied by first mixing it with a suitable solvent and then dispensing it along the periphery of the device where it can be drawn in between the device and substrate by capillary action.
Although the above techniques have been quite successful, there still remains room for improvement in extending the fatigue life.